(A) Field of the Invention
The present invention relates to a trace compression method for a debug and trace interface of a microprocessor.
(B) Description of the Related Art
The rapid advancement of the semiconductor technology has enabled the ability of fabricating the system-on-chip (SOC) device in a single silicon. Because of the continuously growing complexity of the integration, the design verification has become one of the most severe challenges.
The increasing demand of the pre-silicon design verification makes it an urgent need during the early design stage. Traditional design verification examines the difference among the design specification and various levels of design descriptions, e.g., the register-transfer level (RTL), gate-level, and transistor level, etc. However, multiple microprocessors and digital signal processor (DSP) cores are now commonly integrated in an SOC device. In addition, the continuously shortened time-to-market forces the software developing to start before the hardware comes to a real silicon, even when the design specification is not finalized. Therefore, the traditional system debug technique called In-Circuit-Emulator (ICE) is no longer effective for the modern SOC devices. One of the major issues of traditional debug technique is that system debug and verification becomes very complicated. It involves the hardware architecture, software tool chain, applications, and the integration of all of them. To identify the root of bugs among the modern SOC system is difficult. And the other issue is, the iterative simulation of the entire system is time consuming. Several approaches were proposed for coping with the system debug and trace challenges. Among them, ARM Components, Inc. Embedded Trace Macrocell Architecture Specification, 2004, addressed the tracing of the program address and register content with a comprehensive programmer model. Its extended cross-trigger architecture also supports the debug and trace in the multi-core design environment. In 2005, A. Mayer, H. Siebert, and K. McDonald-Maier presented a Package Sized ICE (PSI) for a Multi-Core Debug Support (MCDS) architecture, providing the flexible triggering without the external emulation box. Standard interfaces was presented by A. B. T. Hopkins and K. D. McDonald-Maier in 2006 to decouple the debug support from processor cores and other active data accessing units, which allows debug support being reused across heterogeneous SOC platforms. In addition, the debug and trace of the on-chip communication is also essential for the SOC verification. A multi-resolution trace analyzer was proposed by C.-F. Kao, I.-J. Huang, and C.-H. Lin in 2007, permitting the dynamic selection among different levels of debug abstraction, trading-off between the trace granularity and trace depth. Besides the address and data inside the processors, internal signals deep inside the system are usually inspected for the design debug.